In telecommunications systems that are designed to handle signals with high peak-to-average power ratios (PAPR), Doherty power amplifier architectures have become popular due to their relatively high linearity and efficiency at back-off levels, when compared with other types of amplifier topologies. A conventional two-way Doherty power amplifier includes a class-AB biased main (or “carrier”) amplifier and a class-C biased peaking amplifier in a parallel arrangement. When an input signal has relatively low to moderate power, the main amplifier operates to amplify the input signal, and the peaking amplifier is minimally conducting (e.g., the peaking amplifier essentially is in an off state). During this phase of operation, an impedance transformer in the output combiner network determines the maximum VSWR (voltage standing wave ratio) to which the main amplifier will be exposed. Conversely, as the input signal power increases to a level at which the main amplifier reaches voltage saturation, the input signal is split (e.g., using a 3- or other decibel (dB) power splitter) between the main and peaking amplifier paths, and both amplifiers operate to amplify their respective portion of the input signal. Ultimately, the amplified signals are combined to produce the final amplified output signal.
As the Doherty amplifier input signal level increases beyond the point at which the main amplifier is operating in compression, the peaking amplifier conduction also increases, thus supplying more current to the load. In response, the load line impedance of the main amplifier output decreases. In fact, an impedance modulation effect occurs in which the load line of the main amplifier changes dynamically in response to the input signal power (i.e., the peaking amplifier provides active load pulling to the main amplifier). An impedance inverter at the output of the main amplifier transforms the main amplifier load line impedance to a high value at backoff, allowing the main amplifier to efficiently supply power to the load over an extended output power range.
In some Doherty amplifier topologies, an additional peaking amplifier may be coupled in parallel with the main amplifier and the first peaking amplifier. For example, a 3-way Doherty amplifier, includes a main amplifier and two peaking amplifiers coupled in parallel. In such a topology, the peaking amplifiers are turned on sequentially as power levels increase.
In the practical realization of a conventional Doherty power amplifier, each impedance inverter is supplemented with an offset line to ensure correct phase relationships for optimal load modulation. Each offset line occupies significant printed circuit board (PCB) area, which is contrary to miniaturization efforts. As can be imagined, in 3-way Doherty amplifier, the issue of PCB area occupied by multiple impedance inverters and offset lines is even more pronounced than for a two-way Doherty amplifier. Further, these offset lines, together with the impedance inverters, may restrict the RF bandwidth performance of the Doherty amplifier. Further still, depending on implementation, some transmission line elements may have relatively high characteristic impedances, and this may undesirably limit the power handling capability of an amplifier.